1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device, which includes a semiconductor chip mounted on an interconnect substrate.
2. Related Art
Typical conventional process for manufacturing a semiconductor device that includes a semiconductor chip mounted on an interconnect substrate includes, for example, technologies disclosed in Japanese Patent Laid-Open No. H8-167,629 (1996) and Japanese Patent Laid-Open No. 2003-309,215. In the process described in Japanese Patent Laid-Open No. H8-167,629, a patterned interconnect is formed on a substrate for transfer, and then a resin seal is formed while a condition of a semiconductor chip mounted on the interconnect is maintained, and subsequently, the substrate for transfer is stripped off with a stress to manufacture a semiconductor device.
In a process described in Japanese Patent Laid-Open No. 2003-309,215, as illustrated in FIGS. 42A and 42B, an etchback layer 102 containing Cu as a major constituent and a multiple-layered interconnect board 104 are first deposited on a support substrate 100 composing of silicon or the like (FIG. 42A). Subsequently, stiffening plates 106 are formed on the multiple-layered interconnect board 104, and the etchback layer 102 is removed via a wet etch process from an exposed end thereof, thereby separating the support substrate 100 from the multiple-layered interconnect board 104 (FIG. 42B). Thereafter, semiconductor chips (not shown) are mounted between the stiffening plates 106 on this multiple-layered interconnect board 104 to manufacture a semiconductor device.
However, there is still a room for an improvement in the conventional technologies described above, in view of the following points.
Since the substrate for transfer is strongly adhered with the interconnect layer in the process described in Japanese Patent Laid-Open No. H8-167,629, it is not easy to strip the substrate for transfer off by employing a stress, and an interconnect layer may be damaged by a stress utilized for the stripping.
On the other hand, in the process described in Japanese Patent Laid-Open No. 2003-309,215, the etchback layer 102 is removed from an end thereof via wet etch process.
Therefore, a certain time is required for removing the etchback layer 102, leaving a room for an improvement in reducing the manufacturing cost. Further, since an operation for dipping the multiple-layered interconnect layer 104 in an etchant solution for longer time is required, the multiple-layered interconnect layer 104 may be often damaged.
As such, there are rooms for improvements in view of reducing a manufacturing cost and in view of preventing the interconnect layer from being damaged in the conventional process for manufacturing the semiconductor device.
Further, since the stripping process is carried out by applying a stress over the support substrate in the process described in Japanese Patent Laid-Open No. H8-167,629, the support substrate may be often damaged, and the support substrate can not often be reused. In addition, since the operation for dipping the support substrate in the etchant solution for longer time is required in the process described in Japanese Patent Laid-Open No. 2003-309,215, and an effective reuse of the support substrate can not be achieved.
As described above, there still be a room for an improvement in view of an effective reuse of the support substrate in the conventional process for manufacturing the semiconductor device.